Thesis

Thesis proposals

Open Bachelor's/Master's thesis topics with the group.

Contact directly, guido.masera@polito.it, maurizio.martina@polito.it, alessandra.dolmeta@polito.it, luigi.giuffrida@polito.it

Thesis students

2026 (12)

Samuele Neyroz Automated Hardware Verification Verification Attribute Generation from Multi-Source Specifications Thesis ↗
Roberta Leo Algorithmic and architectural analysis for an in-field reconfigurable receiver decoder for NFC Card-Emulation Thesis ↗
Riccardo Fusari Bus-Level Debug for RISC-V: A Hardware Sniffer and Automated Verification Framework for X-HEEP Thesis ↗
Martina Di Leo Predicting IC design convergence during the ECO stage based on post-route results Thesis ↗
Marco Rausa Multiple ECC design and implementation in multi-bit fault tolerant memories Thesis ↗
Marco Crisologo Energy-Efficiency Framework and Optimization of a Floating-Point Unit for HPC-oriented Architectures Thesis ↗
Manuel Cataldo AI-Optimized Design Verification: Comparative Analysis Thesis ↗
Lorenzo Marino Exploration on a dynamically reconfigurable coprocessor engine Thesis ↗
Giuseppe Cutrera Enhancing Security and Performance of Post-Quantum Cryptographic Signatures on Ramps Thesis ↗
Giulia Solito Reset sequence analysis for deep bug hunting Exploring the use of reset sequences in hardware verification Thesis ↗
Filippo Borghetto PWM-Modulated Digital RF Amplifiers: Principles, Architectures, and Applications Thesis ↗
Damiano Rossetti Restauro digitale dei supporti analogici del patrimonio audiovisivo RAI: analisi critica dell'impiego dell'intelligenza artificiale nella ricostruzione di frame mancanti o estremamente corrotti = Digital restoration of analog media from RAI's audiovisual heritage: critical analysis of the use of artificial intelligence in the reconstruction of missing or extremely corrupted frames Thesis ↗

2025 (33)

Vincenzo Castilletti Riduzione dei tempi di simulazione mediante modellazione analogica comportamentale e semplificazione del DSP negli IP SERDES a 64Gbps = Simulation time reduction through behavioral analog modeling and DSP simplifications in 64Gbps SERDES IP Thesis ↗
Sofia Giannoccaro Design and Implementation of an Embedded Board for Vehicular Connectivity Thesis ↗
Sebastiano Casalaina Hardware design of a high bit rate decoding chain for a full digital ASK demodulator in Wireless Power Transfer application Thesis ↗
Samuele Pasquale Implementation of intermittent-robust computing on RISC-V architecture. RISE: RISC-V Intermittent System Extensions for Batteryless IoT Devices Thesis ↗
Saman Alipour RISC-V Enabled CGRA SystemC Model for AI and ML Applications Thesis ↗
Salvatore Giacomo Lupica Una metodologia efficiente per il test di un SoC basato su microcontrollore, con particolare attenzione alla copertura della memoria Flash integrata. = An efficient approach for testing a microcontroller-based SoC, with focus on embedded flash memory coverage Thesis ↗
Riccardo Carita' Design of an automatic test adapter for digital communications testing in automotive applications Thesis ↗
Pietro Di Maria Advanced techniques for cache replacement policies Thesis ↗
Paolo Palma Analisi del consumo di potenza di circuiti digitali per sensori MEMS basata sull’esplorazione del codice RTL e relativa sintesi logica preliminare = Analysis of power consumption of digital circuits for MEMS sensors based on RTL code exploration and related preliminary logic synthesis Thesis ↗
Paolo Borgis Design of a UVM Based RISC-V model for Digital Functional Verification Thesis ↗
Nico Paninforni Compact Yet Fast: An Efficient d-Order Masked Implementation of Ascon Thesis ↗
Michael Elias Leveraging Quantization and Approximate Computing to Enhance Adversarial Defense in Deep Neural Networks Thesis ↗
Mattia Cozzolino An exploration on connectivity and efficiency in Coarse-Grain Reconfigurable Architectures Thesis ↗
Massimo Giacobbe Behavioral modelling of dinamyc virtual FIFOs Thesis ↗
Manuela Corona Development and customization of an SRAM ECC (Error-Correction-Code) intellectual property (IP) Thesis ↗
Manuel Nannelli Bus Planning to minimize Crosstalk for high frequency design Thesis ↗
Luca Sciolla Progettazione e sviluppo di un sistema embedded ad alte prestazioni per il controllo assi motori e acquisizione dati = Design and Development of a High-Performance Embedded System for Motor Axis Control and Data Acquisition Thesis ↗
Lorenzo Deltetto Design of an Advanced Register Renaming Architecture in a RISC-V Vector Processing Unit Thesis ↗
Lorenzo Capobianco Open Hardware, Hidden Risks: Mitigating passive power side-channel leakage in RISC-V microcontrollers Thesis ↗
Lorenzo Badas Alternative Store Buffers Thesis ↗
Giorgio Iemmolo Architectural Analysis and Performance Optimization of an I2C-to-AHB Bridge for RISCV DMA Thesis ↗
Gabriele Sanna Migration of register verification methodologies, with focus on workflow automation and profiling Thesis ↗
Gabriele Parisi Error Resilience design for Automotive Control Systems Thesis ↗
Gabriele Attanasio Architectural coverage for FEAT_GCS in an AArch64 CPU Thesis ↗
Gabriele Adragna Area and performance evaluation in the physical design of advanced integrated circuits Thesis ↗
Francesco Azzinnari Hardware Architecture for Homomorphic Encrypted Spiking Neural Networks Thesis ↗
Enrico Manfredi Tightly-coupled VS Loosely-coupled accelerators for data compression in space applications: a NOEL-V case study Thesis ↗
Emanuele Bongiovanni Custom RISC-V Processor Development in an FPGA Architecture for On-Board Computing in Space Applications Thesis ↗
Daniele Di Capua Design Space Exploration of Integrated Circuit Floorplans through Area Minimization and ML-Guided Macro Placement Thesis ↗
Claudia Pecorella All-Digital Noise-Tolerant Voltage-Level Detector for Dynamic Configuration of SRAM Read/Write-Assist Circuits Thesis ↗
Chiara Spalluto Evaluation and Integration of a Machine Learning-Based Macro Placer: Impact on Physical Design Flow and Quality Metrics Thesis ↗
Andrea Bonino Analyzing and Extending Instruction Sets for Efficient Cryptographic Computation Thesis ↗
Alessia Casella Evolution of video codecs: a comparative analysis of HEVC, VVC, AV1, and AVM Thesis ↗

2024 (49)

Vincenzo Pio Elia Progettazione di un Adattatore di collaudo automatico per test in potenza di applicazioni in ambito avionico = Design of an Automatic Test Adapter for power testing for avionic application Thesis ↗
Valeria Piscopo Design of a true random number generator for post-quantum cryptography Thesis ↗
Taus Enrico FPGA implementation of a frequency estimator for RADAR localization applications Thesis ↗
Stefano Rizzello Progettazione digitale di compressori approssimati 4:2 per interfacce seriali a 112Gps in tecnologia FinFET = Digital design of 4:2 approximate compressors for 112Gps serial interfaces in FinFET technology Thesis ↗
Simone Romeo ARISE: Integration of an Approximate and Reconfigurable Spatial Array on a RISC-V-Based Platform Thesis ↗
Roman Ali Develop a UVM Metric Driven Verification Environment for Mixed Signal Simulation Thesis ↗
Roberto Capruzzi Exploring Power Improvement Features of Advanced Physical Implementation Flow Thesis ↗
Riccardo Giunti Development of a Monitor IP in a Power Line Communication Modem Thesis ↗
Riccardo Cuccu Unit Testing as a Foundation for Refactoring in Embedded Systems: A Case Study on Qualcomm Cloud AI 100 Thesis ↗
Pietro Romeo Design of an optimized FHOG architecture with Vivado HLS Thesis ↗
Pietro Fagnani RTL UNR code analysis for verification closure applied to digital designs Thesis ↗
Nicolo' Carpentieri Designing and Evaluating Mapping of CNN layers on an edge-CGRA Thesis ↗
Mattia Castagno From minutes to millennia: enhancing power analysis resistance in AES and ASCON Thesis ↗
Mario Porcaro Exploring the impact of RCQ approach in an unrolled LDPC decoder Thesis ↗
Maria Elena D'Agostino LUNA: Learning-based Unified Network Allocation AI-based NoC workload optimization Thesis ↗
Marco Rosa Gobbo Design of a Coverage-driven Reinforcement Learning Framework for RISC-V Functional Verification Thesis ↗
Marco Chiarle Scalar Cryptography Extensions for STxP5 Thesis ↗
Marco Bracchetti Hardware Convolutional Neural Network based on Residue Number System Thesis ↗
Luigi Tedone Development of a high-throughput floating-point CORDIC architecture for automotive applications Thesis ↗
Luigi Asquino I3C® Controller for Sensor Hub feature in MEMS sensors Thesis ↗
Luca Scalenghe Vegetation index for crop monitoring from multi temporal SAR data Thesis ↗
Luca Esposito ADC Testing: Comparison between new test methodologies and standard ones Thesis ↗
Luca D'Elia Quantization Reconstruction Based LDPC Decoders Thesis ↗
Lorenzo Leone A reduction-capable AXI XBAR for fast M-to-1 communication Thesis ↗
Klides Kaba Core Concurrency in multi-core system and scheduler development for STRED architecture Thesis ↗
Ivan Biundo Integration of LEN5, a RISC-V Out-of-Order Microprocessor, Inside a Low-Power, Heterogeneous System on Chip Thesis ↗
Isacco Delpero High-Throughput LDPC Multi-Decoder Exploration with novel Quantization and Reconstruction Method Thesis ↗
Giuseppe Silvestri Automatic detection of timing-violating, non-automatically-fixable paths Thesis ↗
Giuseppe D'Aquino Metodologia di Test per Machine Learning Core (MLC) in sensori MEMS = Testing methodology for Machine Learning Core (MLC) in MEMS sensors Thesis ↗
Gioele Arcoleo Design of an automatic test adapter for AC power testing of multi-voltage switching power supplies Thesis ↗
Giada Cappelletti Generation and verification of timing constraints within the digital implementation flow for the Static Timing Analysis of ASICs Thesis ↗
Giacomo Catena Progettazione RTL di una IP digitale riconfigurabile = RTL Design of a reconfigurable digital IP Thesis ↗
Gabrielegiovanni Montalbano Digital Filters Design Automatization for DS-ADCs Applications Thesis ↗
Francesco Pio De Malde' Implementation of RISC-V Instruction Set Extensions Thesis ↗
Federica Bader Design and integration of a RISC-V based accelerator for Ascon Thesis ↗
Fabrizio Cavallone Design of an integrated circuit for critical particle detection application Thesis ↗
Enrico Longo Studio, implementazione e verifica in ambiente UVM di algoritmi embedded per sensori MEMS = Study, Implementation, and Verification in UVM Environment of Embedded Algorithms for MEMS Sensors Thesis ↗
Emilio Stante Utilizzo delle tecniche di Machine Learning per ottimizzare e accelerare le regressioni di test randomici = Using Machine Learning to Optimize and Accelerate Random Regression Testing Thesis ↗
Davide Muscia Implementation and validation of a hardware countermeasure against fault injection attacks Thesis ↗
Davide Ferraro UVM testbench development for I2S protocol verification Thesis ↗
Davide Altamore FPGA implementation of a vehicles detector Thesis ↗
Claudio Clemente SNAX-CGRA: Ottimizzazione a livello di sistema di un processore CGRA per l'accelerazione efficiente dell'IA = SNAX-CGRA: System-level Optimization of a CGRA Processor for Efficient AI Acceleration Thesis ↗
Carmelo Barbagallo Study and implementation on FPGA of a new Baseband Datapath and Correlator for GNSS applications Thesis ↗
Bianca Maria Perra Investigation on RAM access patterns for power improvements Thesis ↗
Andrea Marenco Design of Approximate Digital Circuits on Advanced Semiconductor Technologies Thesis ↗
Alessio Sanna Low-power radar-based system for materials and objects recognition Thesis ↗
Alessio Caviglia Lightweight Vector Extension for Efficient Neural Network Inference on RISC-V Thesis ↗
Alessandra Ricci Characterization and Translation of the PSI5 Protocol between ATE and DUT Thesis ↗
Abdallah El Mouaatamid Additive Fast Fourier Polynomial Multiplier For Code Based Algorithms Thesis ↗

2023 (36)

Tommaso Ricci Implementation of a RISC-V based microprocessor architecture for NFC communication Thesis ↗
Tiziano Carnevale Miglioramento delle prestazioni dei moderni codificatori video con reti neurali = Improving modern video encoders performances with neural networks Thesis ↗
Stefano Moncalvo Definition of a verification flow for High-Level Synthesis IPs: Case study on functional coverage applied to High Level Synthesis blocks in a C++ and Universal Methodology environment Thesis ↗
Simone Valente Generalized UVM testbench framework for verification of eFPGA devices Thesis ↗
Roberta Fiandaca Power and Area Optimization in Neural Receivers Thesis ↗
Raffaele Virgilio Testing and characterisation of DXPE201 Pin Electronics board Thesis ↗
Paolo Giordano IR-Drop Aware Placement Refiner in Place and Route Design Thesis ↗
Muhammad Afnan Aftab Modeling for Mixed-Signal Simulations Thesis ↗
Michelangelo Miceli A Coherence-Capable Write-Back L1 Data Cache for Ariane Thesis ↗
Mattia Mirigaldi Integration and optimization of a RISC-V based Keccak accelerator Thesis ↗
Matteo Caravaggio A new tool for the full digital flow Thesis ↗
Massimo Emiliano Design of a Spatial Array with Run-Time Reconfigurable Approximate Processing Engines Thesis ↗
Marcos Ricardo Lawrie Design, analysis, and verification of a generic and optimum upsampler by 2 for a Wi-Fi 7 ASIC IP Thesis ↗
Marco Chiavello Development of a Workflow for Power Analysis at RTL-level Design Thesis ↗
Luca Pulvirenti Overcoming Limitations of Static Timing Analysis through Single-Path-Based Transistor Level Simulations in Multi-Power-Domain ASICs for MEMS Sensors Thesis ↗
Lorenzo Ottino Capacità di Verifica con Auto-Test per un Microcontrollore Integrato tramite UVM e Firmware = Self-Checking Verification Capability for an Integrated Microcontroller by UVM and Firmware Thesis ↗
Giovanni Pollo Resilience analysis of FPGA-based Dataflow accelerators Thesis ↗
Gioele Sineo Binary Edward Elliptic Curve CryptoCore Accelerator Thesis ↗
Gaetano Maria Raia Formal Verification Techniques to Check Functional Equivalence between High-Level C Models and RTL Implementations using Jasper C2RTL Thesis ↗
Francesco Gallareto Design digitale di un Viterbi Detector in tecnologia FinFET a 3 nm = Digital design of a Viterbi Detector in 3 nm FinFET technology Thesis ↗
Francesco Enrico Brambilla Modeling and implementation studies of pixel readout architecture for on-chip processing in High Energy Physics applications Thesis ↗
Francesco Dilevrano Serial bit accelerator with sparsity managment Thesis ↗
Francesco Dell'Atti Integrated circuit Back-End of line analysis and modeling for future node pathfinding Thesis ↗
Flavia Guella HERMIONE: a Co-design Methodology for Layer-wise Approximation of Neural Networks on RISC-V Thesis ↗
Federico De Sario Sviluppo Software Per Dispositivi Medici Impiantabili Per Applicazioni Prostetiche = Software Development for Implantable Medical Devices for Prosthetic Applications Thesis ↗
Federica Bongo UVM Environment for I3C Target Device Thesis ↗
Eugenio Ressa An Efficient Hardware Accelerator for Class Incremental Deep Neural Networks Thesis ↗
Davide Milone Expansion board for digital out channels in HIL simulator controlled by CAN protocol Thesis ↗
Davide Guarini Asynchronous State Machine : State of the Art, General Solution for Testing and Automation of Testing Environment Creation Thesis ↗
Daniele Crimi A Microprocessor with customizable Instruction set to improve performance and power consumption Thesis ↗
Claudia Golino Bus Network Integration for Enhanced SoC Performance and Power Consumption - Optimization of Tailored On-chip Interconnection for Low Power Digital System Thesis ↗
Christian Vespo VLSI architectures optimized for the computation of floating-point transcendental functions Thesis ↗
Andrea Amato C-model based verification of a generic IP: an automatic UVM based approach for the functional verification of RTL designs through correspondence checking with a reference C??model Thesis ↗
Alessio Cicero Power and Area Optimization of a Neural Network-Based Digital Pre-Distorter for RF Power Amplifiers Thesis ↗
Alessandro Barrera A Design Space Exploration Tool for LDPC Decoder Architectures in 5G NR Applications Thesis ↗
Alessandra Vignoli WinoAdapt: End-to-End Winograd-based FPGA accelerator for Quantized Convolutional Neural Networks Thesis ↗