Research

The EDGE Group is a research group at the VLSI Lab, Dipartimento di Elettronica e Telecomunicazioni (DET), Politecnico di Torino, working on energy-efficient embedded systems, RISC-V platforms and hardware security.

The group designs custom RISC-V cores and SoC platforms, hardware accelerators for cryptography — including post-quantum schemes — and for AI/edge inference, and the EDA flows needed to bring them to silicon and FPGA. Recent projects include CHIMERA and HORCRUX (cryptographic accelerators), LEN5 (an out-of-order RISC-V core) and Mage-and-Rogue (a CGRA for AI acceleration); the Projects page tracks the full, live list.

The group is active at RISC-V Summits and similar venues, and collaborates with other academic labs and industry partners.

RISC-V platforms and cores

The group designs custom RISC-V cores and the SoC platforms around them, from the in-order pipelines used in teaching to LEN5, an out-of-order superscalar core, and X-HEEP, an open-source microcontroller platform used as the base for several chip tape-outs including POLHEEPO.

Hardware security and cryptography

Hardware accelerators for cryptography, with a focus on post-quantum schemes (CRYSTALS-Kyber, Ascon) and the RISC-V ISA extensions and coprocessors needed to run them efficiently — CHIMERA, HORCRUX, LOKI and ATHOS are recent examples. Work also covers side-channel analysis and true random number generation.

EDA and design tools

Digital design flows to bring the group’s cores and accelerators from RTL to FPGA and silicon, together with the internal tools needed to support them — testbenches, SBST and system-integration flows, and the scripts that automate synthesis and place-and-route.