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It’s called Polheepo — flexible, customizable, and built for businesses: the new chip developed by DET, Politecnico di Torino, as part of the Fondazione SERICS project harnesses the potential of the open RISC-V architecture to adapt to specific production needs, overcoming the limits of traditional devices, which are often closed and hard to modify.

🤖 Currently in the testing phase, Polheepo integrates accelerators for artificial intelligence and post-quantum cryptography, making it suitable for edge, embedded, and low-power applications across multiple sectors. After the initial baseline tests, experiments are now underway on engineered boards, with possible applications in the biomedical and agricultural fields.

Read more on #PoliFlash 👇

The World RISC-V Days Turin 2026 talks are finally live on our YouTube channel! 🎥

#RISCVEverywhere

World RISC-V Days Turin was organized by Alessandra Dolmeta and Luigi Giuffrida — the recordings include Luigi’s own presentation, so don’t miss it.

Check them out 👇

Prof. Maurizio Martina, professor of electronics at Politecnico di Torino, reports to SIE — the Italian Electronics Society — that, thanks to the PNRR SERICS project and with the technical support of Fondazione Chips-IT, a chip in TSMC 65 nm technology has been sent to fabrication.

The chip, named Polheepo, is based on a RISC-V processor together with several accelerators for artificial intelligence and post-quantum cryptography.

To learn more, we’re sharing the article published by Fondazione SERICS 👇